1. Field of the Invention
The present invention relates to semiconductor memory and in particular to a two transistor flash EEPROM cell for use in low-voltage, low-power, high-speed, and high-density applications, such as complex programmable logic devices.
2. Description of the Related Art
Prior art Flash memory technology used in applications for devices, such as PLD (programmable Logic Device), PAL (programmable array logic) and EPLD (erasable programmable logic device), are two transistor memory cells comprised of an NMOS nonvolatile memory device and an NMOS access device. These two transistors are connected in series to form the basic flash memory cell for programmable logic devices. The NMOS nonvolatile memory device of prior art is an asymmetric device with respect to the source and drain as well as operating conditions. A high voltage is required across the drain and source region during programming which requires a longer channel gate length to prevent punch through. This causes a physical limitation on how small the cell can be made and in turn limits the use of the cell in ultra high integration levels of the flash memory below 0.18 um technology.
U.S. Pat. No. 6,108,239 (Sekariapuram et al.) is directed toward a compact nonvolatile programmable memory cell which has a substantially transverse or vertical channel relative to the surface of the semiconductor substrate. In U.S. Pat. No. 6,078,521 (Madurawe et al.) a nonvolatile memory cell is directed toward a compact layout and a high logic output voltage. In U.S. Pat. No. 5,914,904 (Sansbury) is directed toward a nonvolatile memory cell that has a read device, a program device and a tunnel diode. In U.S. Pat. No. 5,904,524 (Smolen) a device and method is directed toward an EEPROM device that has a self aligned tunnel window with low gate capacitance and avoids defects caused by field oxide induced stress in the tunnel oxide. In U.S. Pat. No. 5,914,514 (Dejenfelt et al.) a flash EEPROM cell is directed toward a two transistor cell for high speed and high density PLD applications. The storage transistor is directed toward preventing problems with over erase and punch through, and allows scaling the gate length to allow 5V cell programming.
In U.S. Pat. No. 5,862,082 (Dejenfelt et al.) a device is directed toward a flash EEPROM cell that has two transistors with one transistor being a floating gate type device with asymmetric source and drain. In FIG. 1 is shown a cross sectional view of prior art for aflash EEPROM cell 100 similar to that of U.S. Pat. No. 5,862,082. The flash EEPROM cell includes a nonvolatile memory transistor 101 and an access transistor 102. The nonvolatile memory transistor 101 is fabricated within a p-well 103 and is a stack type double poly transistor, which includes a thin tunnel oxide film 108, a floating gate 109, an interpoly dielectric layer 110, a control gate 113, n+ source region 123, n+ source/drain region 122 and nxe2x88x92 type region 124. The access transistor 102 is fabricated within a p-well 103, which includes a source/drain region 122, n+ drain region 121, a gate dielectric layer 111 and an access gate 112. The P-well 103 is formed within an n-well 104, which is formed on a p-substrate 105. A field oxide layer 120 is formed over the upper surface of the substrate 105. An N+ type region 106 is formed in the n-well 104 creating a contact region for the N-well. A P+type region 107 is formed in p-well 103 creating a contact region for the P-well.
FIG. 2 of the prior art is a circuit diagram illustrated as a 2xc3x972 array 600, formed by a plurality of identical flash EEPROM cells 601, 602, 603 and 604, which are comprised of the flash EEPROM cell 100 . Each column of cells has separate source lines 631 and 641 and drain bit lines 632 and 642 for high-speed PLD applications. Lines 611 and 621 connect to the control gates of the storage transistors of cells 601 and 602, and cells 603 and 604 respectively. Lines 612 and 622 connect to the access gates of the access transistors of cells 601 and 602, and cells 603 and 604 respectively.
FIG.3 is a plane view of prior art of the flash EEPROM cells 601 to 604 of array 600, and corresponding to the circuit diagram in FIG. 2. Control gate lines 611 and 621 run horizontal across the plane view of the cells connecting to the control gates of the storage transistors of cells 601 and 602, and cells 603 and 604 respectively. Similarly access lines 612 and 622 run horizontally across the plane view of the cells connecting to the gates of the access transistors of cells 601 and 602, and cells 603 and 604 respectively. Source lines 631 and 641 run vertically across the plane view connecting to the sources of the storage transistors of the EEPROM cells 601 and 603, and cells 602 and 604 respectively. Similarly bit lines 632 and 642 run vertically across the plane view connecting to the sources of the storage transistors of the EEPROM cells 601 and 603, and cells 602 and 604 respectively.
FIG. 4 is a table for the prior art illustrating the voltage conditions for program, program inhibit, erase and read operation for array 600. Both erase and program operations use the Fowler-Nordheim tunneling. The electrons are injected into the floating gate of the storage transistor of the cells by channel-erase operation which increases the threshold voltage Vt) of the storage transistor. The electrons are extracted out of the floating gate of the storage transistor by an edge-program operation which decreases Vt. The erase operation is performed in a blanket mode. All the cells 601-604 in array 600 are erased simultaneously. A high voltage of 8 to 10 volts is applied to the control gate word lines 611 and 621, and a negative high voltage of xe2x88x928 to xe2x88x9210 volts is applied to source lines 631 and 641. At the same time, the same negative high voltage xe2x88x928 to xe2x88x9210 volts is applied to p-well 103, and Vcc supply voltage of 3.3 volts is applied to n-welll 04. Thus the threshold voltage Vt of the storage transistor of the cells is increased for the erase operation.
Continuing to refer to FIG. 4, a program operation is performed bit by bit on each word line. For example, cell 601 is programmed and cell 602 is program inhibited by applying a voltage of xe2x88x927 to xe2x88x9211 volts to the control gate word line 611 and applying a voltage of 8 volts is to the access gate 612. The source lines 631 and 641 are maintained at a high impedance state, and a voltage of 5 to 8 volts is applied to the bit line 632 with 0 volt applied to the bit line 642. P-well 103 is maintained at 0V and the n-well 104 is maintained at the Vcc supply voltage, 3.3 volts. As a result, cells 601 and 602 are placed in the program and program inhibition mode, respectively.
Continuing to refer to FIG. 4, the two-transistor flash EEPROM cell of prior art created with an n+ source/drain region 122 and an nxe2x88x92 type region 124 that are made to be much deeper than the n+ source junction 123, which is surrounded with lightly-doped N-implant to reduce the peak electrical field generated during drain-edge-program operation. For programming purposes, it should be noted that there is a reverse bias voltage between nxe2x88x92 type region 124 and p-well 103. As a result of the negative high voltage applied to the gate of the memory cell, electron-hole pairs will be generated and holes are accelerated onto the floating gate under the high electrical field. A certain amount of holes will be trapped in the tunnel oxide, and will degrade the oxide after cycling.
The memory cell of prior art is made non-symmetrical with respect to source and drain junctions in terms of cell structure and operating conditions. A high voltage of more than 5V across lightly doped N implant drain region and source region during program operation is required. Therefore, the prior art cell of FIG. 1 through FIG. 4 needs a longer channel gate length to prevent punch-through. Otherwise, the impact of punch-through is the degraded efficiency in program operation. The prior art has limitations in shrinking the length of the cell for ultra-high integrated flash memory below 0.18 um technology.
An objective of the present invention is to use a fully symmetrical, scaleable Flash EEPROM memory cell having a storage transistor coupled in series with an access transistor, and which may be used to form compact flash arrays for programmable logic device;
Another objective is to replace the edge-program operations in prior art by channel program operation to remove the high voltage drop across the channel region of the storage transistor of the cell. Such removal of the voltage gradient across source and drain permits the use of a shorter channel length for high-density applications, such as in complex programmable logic devices (CPLDs);
Still another objective of the invention is to provide channel erase by reducing the threshold of flash EEPROM cell with immunity from the over erase problem;
Yet another objective of the invention is to provide a preferred voltage for non-selected word lines for a channel program operation so that the disturbance of the Vt of non-selected cells can be eliminated or substantially reduced;
Yet another further objective of the invention is to provide the preferred voltages for word lines, bit lines, source lines and P-wells so that the aforesaid drawbacks of asymmetrical cell can be eliminated and replaced by a highly scaleable symmetrical cell;
Still another objective of the invention is to provide the preferred voltages for word lines, bit lines, source lines and P-wells so that the aforesaid drawback of channel punch-through can be eliminated and high current program and erase operations can be reduced;
Still another further objective of the invention is to provide the preferred voltages for word lines, bit lines, source lines and P-well so that the aforesaid drawback of low cycling can be improved with high endurance.
Still yet another objective of the invention is to provide a two-transistor cell with over erase immunity for a simplified on chip state machine without program and erase verifications;
Still yet another objective of the invention is to provide a two-transistor cell with a floating gate device fully compatible with the access device and any peripheral NMOS single poly devices in terms of process step and device structure.
The present invention provides a highly scalable, two-transistor, Flash EEPROM cell with a fully symmetrical source and drain structure. The two-transistor cells are comprised of one NMOS floating-gate nonvolatile memory (NVM) and one NMOS access device. These two transistors are connected in series to form a flash cell in accordance with the present invention. A plurality of these two-transistor cells are used to form a matrix array with a plurality of columns and rows. The columns are comprised of metal bit lines and metal source lines coupling to drains and sources of the two-transistor cells. The bit lines and source lines are decoded by a bit line decoder and a source decoder, respectively, and run vertically in parallel through flash cell array. The rows are comprised of a plurality of word lines and access lines. The word lines are connected to the gates of NVM devices of the two-transistor cells, and the access lines are connected to the gates of access devices of two-transistor cells. The word lines and access lines run horizontally across the flash cell array. The bit lines are connected to sense amplifiers and source lines are connected to source line decoders. The word lines and the access lines are driven by X-decoder and access decoders. The preferred two transistor flash cell and the cell array are targeted for low-voltage, high-speed and high-density programmable logic devices, comprising PLD, PAL, and EPLD applications.
Unlike the prior art flash technology used in PLD, PAL and EPLD, the two-transistor flash cell utilizes the preferred Fowler-Nordheim (FN) channel erase and FN channel program methods to allow a fully symmetrical cell structure with ultra-high cell scalability and ultra-low program and erase current. With the two-transistor cell structure, the cell of the present invention provides a solution to fully eliminate the conventional over erase problem that occurs in one transistor flash cells. This is because the access transistor will not conduct current even though the NMOS floating gate nonvolatile memory is over erased. In addition, the flash cell of the present invention can be made to avoid punch through and disturbance problems particularly in sub-micron flash technology by using the preferred channel erase and channel program operations.
The main advantage of the channel erase and the channel program is the elimination of the high voltage drop across the drain and source of the flash cells during program and erase operations. As a result, the channel length of the flash cell is no longer limited by erase and program operations and is only determined by the read operation. Conventionally, read operations in flash memory is designed to operate with less than 1V across the drain and source nodes; therefore, the length of the flash cell of the present invention can be easily shrunken producing a high cell scalability. Also a large read current can be achieved in accordance with the present invention.
The erase and program operations are performed in a manner without any program and erase verifications in a two transistor flash cell. A very simple on-chip state-machine can be accomplished to control the reduced on-chip operations for the applications requiring in-system re-programmability. According to the present invention, the charge storage gate electrode (floating gate electrode) of the nonvolatile cell is formed on the surface of an active region by means of a polysilicon layer on top of a first insulating film. A control gate electrode is formed on the surface of the charge storage gate electrode by means of a polysilicon layer on top of a second insulating film. The bulk of the cell can be either formed on P-substrate or a P-well within a deep N-well on P-substrate.